Comments

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Address bus display

Address entry switches

Construction notes for the ALU section

ALU function decoding

Adder control & enable

Zero detect

Adder

Logic unit

AND display & enable

OR display & enable

XOR display & enable

NOT display & enable

SHL display & enable

Condition register

ALU result bus & display

Clock to produce pulses for front panel operations

Pulse sequences produced by auxiliary clock

Parts needed to build RC-3

Pin assignments for interconnection cables

Clock pulse generator

Pulse relationships for clock generator

Instruction decoder and display

Control signal generation for instruction fetch and increment

Control signal generation for load and store instructions

Control signal generation for SetAB, IncXY, and ALU instructions

Control signal generation for Mov8, Mov16, and Misc instructions

Control signal generation for GoTo instructions

Front panel display of generated control signals

Front panel display of generated control signals

Front panel display of generated control signals

Front panel display and generation of control signal inputs

Cross-32 configuration file for RC-3

Assembly listing for cross-assembler test file

File showing examples of allowed cross-assembler instructions

Data bus display

Data entry switches

Current revision level of all documents

Front panel connector printed circuit board as-built dimensions

Front panel (top through 8U)

Front panel (8U through 21U)

Front panel (21U through 33U)

Dimensioned front panel layout for ALU section

Dimensioned front panel layout for Clock section

Dimensioned front panel layout for Control section

Dimensioned front panel layout for Operators Panel section

Dimensioned front panel layout for Power section

Dimensioned front panel layout for Register section

Pulse sequences for LoadAddress/Examine/Deposit

Pulse sequences for ExamineNext and DepositNext

Control signal generation for front panel operations

Front panel printed circuit board A design requirements

Front panel printed circuit board B design requirements

Front panel printed circuit board B design requirement

Front panel printed circuit board B cuts & jumpers for FPops row

General notes concerning drawing interpretation

Incrementer bits 15-8

Incrementer bits 7-0

Pulse sequences for Fetch/Increment, Mov, ALU, and IncXY instructions

Pulse sequences for SetAB, Mov16, Misc, Load, and Store instructions

Pulse sequences for GoTo/SetM/Call/BC family of instructions

Logic and display interconnect cabling

Power cabling

Chart of the 19 pulses required for normal operations

Data bus to memory

Memory to data bus

Address bus to memory (bits 14-8), chip select & output enable control

Address bus to memory (bits 7-0)

Memory control

Chip interfaces

12 VDC distribution

AC switching, power supplies, and fans

Driver for Parallel Printer

Physical layout for printer driver display panel

Front panel display of sequencer states

Generation and display of pulses P-A through P-J

Generation and display of pulses P-K through P-T

Display and control of abort signals

Relay mounting rail assignments

Description of instruction set

Op code map of RC-3 instruction set

General purpose register

General purpose register and input to ALU

General purpose register and input to ALU

General purpose register

Increment register control and bits 15-8

Increment register bits 7-0

Instruction register

Jump register control

Jump register bits 15-8 (J1 register)

Jump register bits 7-0 (J2 register)

Memory register control

Memory register bits 15-8 (M1 register)

Memory register bits 7-0 (M2 register)

Program counter control and bits 15-8

Program counter bits 7-0

XY register control

XY register bits 15-8 (X register)

XY register bits 7-0 (Y register)

Construction log

Relay connector printed circuit board design requirements

Relay layout for Clock/AuxClock

Relay layout for Sequencer

Relay layout for Control

Relay layout for registers A-D

Relay layout for register XY

Relay layout for register M

Relay layout for ALU

Relay layout for memory interface

Relay layout for register J

Relay layout for Instruction Register

Relay layout for Program Counter

Relay layout for INC register and Incrementer

Sequencer stages 0-7 and Abort8 relay

Sequencer stages 8-15 and Abort10/Abort12/Abort14 relays

Sequencer stages 16-23

Pulses generated by sequencer stages 0-8

Pulses generated by sequencer stages 9-16

Pulses generated by sequencer stages 17-23

Pulse sequences for Abort8, Abort10, and Abort12 transitions

Pulse sequences for Abort14 transition

Architecture drawing, courtesy of Harry Porter

Guide to understanding machine operations